1. Field of the Invention
This invention relates to the decoding of instructions of two types. In particular, the invention relates to the decoding of the multimedia enhancement technology such as MMX technology instructions and non-multimedia enhancement technology instructions using alias encodings of the data size field.
2. Description of Related Art
In a typical microprocessor architecture, the instruction decoder is responsible for decoding the instructions fetched from the memory. In a microprogrammed architecture, the instruction Operation Code (Opcode) fetched from the memory is referred to as the macro-instruction. This macro-instruction is represented by a macro-opcode which is translated by the instruction decoder into micro-instructions or micro-operations (.mu.OP). The .mu.Ops correspond to the primitive or elemental steps in the execution of the macro-instruction.
In the prior art Intel.RTM. architecture, the .mu.Ops are classified into groups according to their formats and types. A portion of the .mu.Op, called micro-operation code (.mu.Opcode) is used to determine the type of operation and the group. At the decoding stage, the .mu.Ops are sent to appropriate ports for execution. In a prior art INTEL.RTM. Architecture microprocessor, there are 5 ports connected to appropriate execution units for executing the .mu.Ops. Each port is allocated specific hardware resources to perform the specified operations. For example, port 0 is for integer and floating-point operations, port 1 is for branch and integer operations, port 2 is for load operations, port 3 is for store address operation, and port 4 is for store data operation.
The multimedia enhancement technology instructions are designed for multimedia applications which include many parallel operations. There are a number of multimedia enhancement technology instructions that need to go to port 1 for execution. However, the field reserved for port 1 instructions is fixed and cannot be expanded for decoding the additional enhancement instructions. This lack of decoding space creates further problems if more enhancement instructions are needed in the future.
In addition, there is a large amount of software that has been developed for the INTEL.RTM. Architecture microprocessors including compilers and assemblers that generate the machine codes. To maintain compatibility with these software packages, it is preferred that the machine codes are not recoded to accommodate the additional enhancement instructions.
It is therefore desirable to have a method or apparatus for decoding the enhancement instructions on port 1 while maintaining compatibility with earlier architectures.